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? semiconductor components industries, llc, 2010 november, 2010 ? rev. 9 1 publication order number: nlast44599/d nlast44599 low voltage single supply dual dpdt analog switch the nlast44599 is an advanced cmos dual ? independent dpdt (double pole ? double throw) analog switch, fabricated with silicon gate cmos technology. it achieves high ? speed propagation delays and low on resistances while maintaining cmos low ? power dissipation. this dpdt controls analog and digital voltages that may vary across the full power ? supply range (from v cc to gnd). the device has been designed so the on resistance (r on ) is much lower and more linear over input voltage than r on of typical cmos analog switches. the channel ? select input structure provides protection when voltages between 0 v and 5.5 v are applied, regardless of the supply voltage. this input structure helps prevent device destruction caused by supply voltage ? input/output voltage mismatch, battery backup, hot insertion, etc. the nlast44599 can also be used as a quad 2 ? to ? 1 multiplexer ? demultiplexer analog switch with two select pins that each controls two multiplexer ? demultiplexers. ? select pins compatible with ttl levels ? channel select input overvoltage tolerant to 5.5 v ? fast switching and propagation speeds ? break ? before ? make circuitry ? low power dissipation: i cc = 2 a (max) at t a = 25 c ? diode protection provided on channel select input ? improved linearity and lower on resistance over input voltage ? latch ? up performance exceeds 300 ma ? esd performance: human body model > 2000 v; machine model > 100 v ? chip complexity: 158 fets ? pb ? free packages are available marking diagrams see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information a = assembly location l = wafer lot y = year w = work week = pb ? free package qfn ? 16 mn suffix case 485g tssop ? 16 dt suffix case 948f 1 t alyw 16 http://onsemi.com 1 16 nlat 4459 alyw 1 16 (note: microdot may be in either location)
nlast44599 http://onsemi.com 2 qfn ? 16 package 1 2 3 75 6 8 9 10 11 12 13 14 15 16 com a no a 0 v cc nc d 1 nc a 1 sab no b 0 com b nc b1 gnd no c 0 com c see tssop ? 16 switch configuration com d no d 0 scd nc c 1 4 function table select ab or cd on channel l h nc to com no to com v cc nc d1 com d no d0 select cd nc c 1 com c no c 0 nc b 1 gnd no b 0 com b nc a 1 com a no a 0 e lect ab 116 2 3 4 5 6 7 8 9 10 11 12 13 14 15 u u com a select ab x1 no a 0 u nc a 1 figure 1. logic diagram tssop ? 16 package u no b 0 u nc b 1 u no c 0 u nc c 1 u no d 0 u nc d 1 select cd x1 u com b u com c u com d 0/1 2/3 0/1 2/3 0 1 2 3 0 1 2 3 figure 2. iec logic symbol
nlast44599 http://onsemi.com 3 maximum ratings symbol parameter value unit v cc positive dc supply voltage 0.5 to 7.0 v v is analog input voltage (v no or v com ) 0.5 v is v cc 0.5 v v in digital select input v oltage 0.5 v i 7.0 v i ik dc current, into or out of any pin 50 ma p d power dissipation in still air qfn ? 16 tssop ? 16 800 450 mw t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias +150 c msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul ? 94 ? vo (0.125 in) v esd esd withstand voltage human body model (note 1) machine model (note 2) charged device model (note 3) 2000 100 1000 v i latch ? up latch ? up performance above v cc and below gnd at 125 c (note 4) 300 ma ja thermal resistance qfn ? 16 tssop ? 16 80 164 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. tested to eia/jesd22 ? a114 ? a. 2. tested to eia/jesd22 ? a115 ? a. 3. tested to jesd22 ? c101 ? a. 4. tested to eia/jesd78. recommended opera ting conditions symbol parameter min max unit v cc dc supply voltage 2.0 5.5 v v in digital select input v oltage gnd 5.5 v v is analog input voltage (nc, no, com) gnd v cc v t a operating temperature range 55 125 c t r , t f input rise or fall time, select v cc = 3.3 v 0.3 v v cc = 5.0 v 0.5 v 0 0 100 20 ns/v device junction temperature versus time to 0.1% bond failures junction temperature c time, hours time, y ears 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 1 1 10 100 1000 failure rate of plastic = ceramic until intermetallics occur figure 3. failure rate vs. time junction temperature normalized failure rate time, years t j = 130 c t j = 120 c t j = 110 c t j = 100 c t j = 90 c t j = 80 c
nlast44599 http://onsemi.com 4 dc characteristics ? digital section (voltages referenced to gnd) symbol parameter condition v cc guaranteed limit unit 55 c to 25 c 85 c 125 c v ih minimum high ? level input voltage, select inputs 3.0 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 v v il maximum low ? level input voltage, select inputs 3.0 4.5 5.5 0.5 0.8 0.8 0.5 0.8 0.8 0.5 0.8 0.8 v i in maximum input leakage current v in = 5.5 v or gnd 5.5 0.2 2.0 2.0 a i off power off leakage current, select inputs v in = 5.5 v or gnd 0 10 10 10 a i cc maximum quiescent supply current select and v is = v cc or gnd 5.5 4.0 4.0 8.0 a dc electrical characteristics ? analog section symbol parameter condition v cc guaranteed limit unit 55 c to 25 c 85 c 125 c r on maximum ?on? resistance (figures 17 ? 23) v in = v il or v ih v is = gnd to v cc i in i 10.0 ma 2.5 3.0 4.5 5.5 85 45 30 25 95 50 35 30 105 55 40 35 r flat (on) on resistance flatness (figures 17 ? 23) v in = v il or v ih i in i 10.0 ma v is = 1 v, 2 v, 3.5 v 4.5 4 4 5 i nc(off) i no(off) no or nc off leakage current (figure 9) v in = v il or v ih v no or v nc = 1.0 v com 4.5 v 5.5 1 10 100 na i com(on) com on leakage current (figure 9) v in = v il or v ih v no 1.0 v or 4.5 v with v nc floating or v no 1.0 v or 4.5 v with v no floating v com = 1.0 v or 4.5 v 5.5 1 10 100 na
nlast44599 http://onsemi.com 5 ac electrical characteristics (input t r = t f = 3.0 ns) guaranteed maximum limit v cc v is 55 c to 25 c 85 c 125 c symbol parameter test conditions (v) (v) min typ* max min max min max unit t on turn ? on time (figures 12 and 13) r l = 300 c l = 35 pf (figures 5 and 6) 2.5 3.0 4.5 5.5 2.0 2.0 3.0 3.0 5 5 2 2 23 16 11 9 35 24 16 14 5 5 2 2 38 27 19 17 5 5 2 2 41 30 22 20 ns t off turn ? off time (figures 12 and 13) r l = 300 c l = 35 pf (figures 5 and 6) 2.5 3.0 4.5 5.5 2.0 2.0 3.0 3.0 1 1 1 1 7 5 4 3 12 10 6 5 1 1 1 1 15 13 9 8 1 1 1 1 18 16 12 11 ns t bbm minimum break ? before ? make time v is = 3.0 v (figure 4) r l = 300 c l = 35 pf 2.5 3.0 4.5 5.5 2.0 2.0 3.0 3.0 1 1 1 1 12 11 6 5 1 1 1 1 1 1 1 1 ns *typical characteristics are at 25 c. typical @ 25, vcc = 5.0 v c in c no or c nc c com c (on) maximum input capacitance, select input analog i/o (switch off) common i/o (switch off) feedthrough (switch on) 8 10 10 20 pf additional applica tion characteristics (voltages referenced to gnd unless noted) v cc typical symbol parameter condition v 25 c unit bw maximum on ? channel 3 db bandwidth or minimum frequency response (figure 11) v in = 0 dbm v in centered between v cc and gnd (figure 7) 3.0 4.5 5.5 145 170 175 mhz v onl maximum feedthrough on loss v in = 0 dbm @ 100 khz to 50 mhz v in centered between v cc and gnd (figure 7) 3.0 4.5 5.5 ? 3 ? 3 ? 3 db v iso off ? channel isolation (figure 10) f = 100 khz; v is = 1 v rms v in centered between v cc and gnd (figure 7) 3.0 4.5 5.5 ? 93 ? 93 ? 93 db q charge injection select input to common i/o (figure 15) v in = v cc to gnd, f is = 20 khz t r = t f = 3 ns r is = 0 , c l = 1000 pf q = c l * v out (figure 8) 3.0 5.5 1.5 3.0 pc thd total harmonic distortion thd noise (figure 14) f is = 20 hz to 100 khz, r l = rgen = 600 , c l = 50 pf v is = 5.0 v pp sine wave 5.5 0.1 % vct channel to channel crosstalk f = 100 khz; v is = 1 v rms v in centered between v cc and gnd (figure 7) 5.5 3.0 ? 90 ? 90 db
nlast44599 http://onsemi.com 6 figure 4. t bbm (time break ? before ? make) output dut 300 35 pf v cc switch select pin 90% output input v cc gnd 90% of v oh gnd figure 5. t on /t off 50% 50% 90% 90% t on t off v oh output input v cc 0 v figure 6. t on /t off dut open 35 pf v cc input 50% 50% 10% t on t off output input v cc 0 v 10% 300 0.1 f t bmm output v out v ol v out v oh v ol dut open v cc input output 300 35 pf v out 0.1 f
nlast44599 http://onsemi.com 7 channel switch control/s test socket is normalized. off isolation is measured across an off channel. on loss is the bandwidth of an on switch. v iso , bandwidth and v onl are independent of the input signal direction. v iso = off channel isolation = 20 log for v in at 100 khz v onl = on channel loss = 20 log for v in at 100 khz to 50 mhz bandwidth (bw) = the frequency 3 db below v onl v ct = use v iso setup and test to all other switch analog input/outputs terminated with 50 output dut input 50 50 generator reference transmitted figure 7. off channel isolation/on channel loss (bw)/crosstalk (on channel to off channel)/v onl 50 v out v in v out v in off on off v out v cc gnd output v in c l dut figure 8. charge injection: (q) v in open output ? 55 ? 20 leakage (na) figure 9. switch leakage vs. temperature 1 i no(off) temperature ( c) 0.01 25 0.001 0.1 70 85 125 i com(on) i com(off) v cc = 5.0 v 10 100
nlast44599 http://onsemi.com 8 figure 10. off ? channel isolation figure 11. typical bandwidth and phase shift 1 0.1 0.01 3.0 30 2.5 4.5 35 figure 12. t on and t off vs. v cc at 25 c v cc (volts) figure 13. t on and t off vs. temp temperature ( c) time (ns) time (ns) figure 14. total harmonic distortion plus noise vs. frequency frequency (khz) figure 15. charge injection vs. com voltage v com (v) thd + noise (%) q (pc) 10 1 100 ? 55 25 125 ? 40 20 15 25 0 034 2 15 t on v cc = 3 v v cc = 5 v 2.5 2.0 1.5 1.0 0.5 0 ? 0.5 v inpp = 5.0 v v cc = 5.5 v v inpp = 3.0 v v cc = 3.6 v 10 5 t off t on (ns) t off (ns) v cc = 4.5 v 3.5 4 30 20 15 25 0 10 5 85 0.01 10 1 0.1 (db) ? 100 0 off isolation frequency (mhz) 100 200 ? 80 ? 60 ? 40 ? 20 v cc = 5.0 v t a = 25 c 0.01 10 1 0.1 100 300 frequency (mhz) phase ( ) bandwidth (on ? response) phase shift v cc = 5.0 v t a = 25 c ? 5 ? 15 ? 35 ? 10 ? 20 ? 30 ? 25 0 +5 +10 +15 (db) 2.0 4.0 6.0 10.0 0 1.0 3.0 5.0 7.0 9.0 8.0
nlast44599 http://onsemi.com 9 0 5 10 15 20 25 30 35 40 45 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 25 c ? 55 c 85 c 125 c 85 c ? 55 c 125 c 0 10 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 25 c ? 55 c 85 c 25 c 125 c 0 10 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 2.0 1.0 3.0 4.0 5.0 6.0 temperature ( c) figure 16. i cc vs. temp, v cc = 3 v and 5 v i cc (na) 80 100 60 40 20 0 figure 17. r on vs. v cc, temp = 25 c v is (vdc) figure 18. r on vs temp, v cc = 2.0 v r on ( ) r on ( ) figure 19. r on vs. temp, v cc = 2.5 v v is (vdc) figure 20. r on vs. temp, v cc = 3.0 v v is (vdc) r on ( ) r on ( ) ? 40 60 80 20 0 100 ? 20 120 v cc = 2.0 v v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.5 v v cc = 3.0 v v cc = 5.0 v 10 1 0.1 100 0.01 0.001 0.0001 0.00001 figure 21. r on vs. temp, v cc = 4.5 v v is (vdc) 0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 r on ( ) v is (vdc) 25 c ? 55 c 125 c 85 c
nlast44599 http://onsemi.com 10 figure 22. r on vs. temp, v cc = 5.0 v figure 23. r on vs. temp, v cc = 5.5 v 20 15 r on ( ) 10 25 v is (vdc) 5 0 0.0 2.0 1.5 1.0 0.5 2.5 3.0 3.5 4.0 4.5 5.0 25 c 85 c 125 c ? 55 c 20 15 r on ( ) 10 25 v is (vdc) 5 0 0.0 2.0 1.5 1.0 0.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 25 c 85 c 125 c ? 55 c device ordering information device order number device nomenclature package type shipping ? circuit indicator technology device function package suffix tape and reel suffix nlast44599dt nl as 44599 dt tssop ? 16* 96 unit / rail nlast44599dtr2 nl as 44599 dt r2 tssop ? 16* 2500 / tape & reel nlast44599mn nl as 44599 mn qfn ? 16 124 unit rail nlast44599mng nl as 44599 mn qfn ? 16 (pb ? free) 124 unit rail nlast44599mnr2 nl as 44599 mn r2 qfn ? 16 2500 / tape & reel nlast44599mnr2g nl as 44599 mn r2 qfn ? 16 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd801 1/d. *this package is inherently pb ? free.
nlast44599 http://onsemi.com 11 package dimensions 16 pin qfn case 485g ? 01 issue d 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ l1 detail a l alternate terminal constructions ?? ?? ?? ?? ?? 0.00 0.15
nlast44599 http://onsemi.com 12 package dimensions tssop ? 16 case 948f ? 01 issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ??? ??? ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d.
nlast44599 http://onsemi.com 13 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a s ituation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nlast44599/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative

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